Cmos Circuit to Sense the Value of the Input Power Supply to a Chip
Original Publication Date: 1989-Apr-01
Included in the Prior Art Database: 2005-Jan-27
A circuit is described which monitors the value of the chip supply voltage and signals when the level is above a preset value. Many times in circuit applications it is desirable to not respond to control inputs to a chip during a power up or down cycle. A power up or down cycle is defined as the period of time when the supply voltage to the chip is ramping up to its desired value or ramping down to zero volts. A signal must be generated that indicates when the supply voltage is below a certain value. This signal is used in the control process of the chip to determine the proper response to be taken depending on the state the chip is in. (Image Omitted) The required circuit must respond to the change in the supply voltage when the value drops below a given value but it must not respond for normal supply variations.