High-Performance Unclocked Asynchronous Star Arbitration
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
This article describes an arbitration function for multiple, asynchronous bus masters without the loss in performance usually incurred due to the use of a clock or oscillator within the arbitration logic. Typically, asynchronous bus arbitration logic designs include a clock and some form of dual rank synchronizing latches to align the input bus request signals with each other and to resolve possible metastable latch states occurring during the synchronizing process. Such use of a clock adds a delay equal to half the clock period to the arbitration logic response time. The design being described eliminates the delay by providing the bus arbitration functions without the clock. This design is directed to an asynchronous, multiple master system bus. Many bus masters can share such a bus.