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Existing DRAM Modified to Be a Display RAM Characterized by Bit Steering and Single Carry Look Ahead Functions

IP.com Disclosure Number: IPCOM000034895D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Herrman, BD Vincent, MF [+details]

Abstract

A modified DRAM design is shown which is adaptable to a display random- address memory (RAM) with a bit incrementer. (Image Omitted) The modified DRAM design avoids interaction with precharged internal dynamic nodes by operating on row and column data before activation of the row address select (RAS) and column address select (CAS) signals. This allows setup time to approach existing base DRAM specifications. Also, bit steering and multiplexing (MUX) circuits utilize existing internal signals available in the address receive space, allowing for a compact design. Address incrementer logic is inserted between the address receiver and address generation circuits. Referring to Fig.