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Bit Line/Word Line Boost Circuit

IP.com Disclosure Number: IPCOM000034897D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Ellis, WF Fifield, JA Tomashot, SW [+details]

Abstract

A post sense bit and word line boost circuit design is shown which enhances the margins in advanced DRAMs and protects the cells against alpha particle radiation and leakage induced noise. (Image Omitted) As semiconductor process tolerances improve, greater levels of integration on a chip result. Cell areas and signal margins are reduced and stored "1" levels become more sensitive to alpha particles and leakage induced noise. Implementation of a post sense bit line and word line boost design will minimize this problem. At the beginning of a row address select (RAS) restore, the selected word line is boosted to at least a VT above Vdd and simultaneously the high bit lines are actively clamped to Vdd. This results in a full "1" level being written into the cell. Referring to Fig.