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Functional Use of LSSD a Clock

IP.com Disclosure Number: IPCOM000034915D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Hanna, SD [+details]

Abstract

The design technique to be described minimizes the logic necessary to create a loadable counter in a two-phase clock system. This design technique can also be used for any two port latch where one port is merely for loading from an L2 latch output. The clock generation logic can thereby use the LSSD A (CLKA) or AS clock functionally designing the latch configuration (and the shift path) to conform to the functional design requirements. A single clock can be multiplexed to load or to increment a counter using the described technique. The basic LSSD two-latch pair is shown in Fig. 1. The clock input signals are not included but the L1 latch stages are set by the first clock, CLKA, of a two-phase clock and the L2 latch stages, by the second clock, CLKB.