Error Detection for Pipeline Clocking Circuitry
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
This article describes a system clock design including checking the interconnections between a clock generation module and a data or address pipeline module. It also provides a second check for the clock generation state machine. Some of the clock generation state machine output signals are checked by being independently generated and compared to the signals. The duplication uses a different generation method from the clock generation logic. This described technique is valuable because it is difficult to design error checks for clocking and control signals. The technique is demonstrated for two different applications. The master clock generator has one feedback signal from the slave that it compares with its internally generated prediction of what the feedback should be.