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Asynchronous Digital Filter Interface Design Disclosure Number: IPCOM000034921D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27

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Vogelsberg, RE [+details]


This article describes an interface between an unclocked (asynchronous) input signal and a clocked digital subsystem. It provides sampling and synchronization of the input signal through two levels of clocked latches which, in turn, align the input signal with the digital subsystem clocks and resolve any potential metastable latch states that may occur during the synchronizing process. A feature of this design is additional, parallel logic that provides noise rejection capabilities to the synchronizing circuit. Many logic designs require an asynchronous input signal to be synchronized to a locally clocked logic subsystem, accompanied with a requirement to remove noise from the input prior to sampling the input signal.