Variable Duration Microprocessor Clock Generation
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27
This article describes a microprocessor clock generator to interface with memory or peripheral devices having different or variable length access times without the loss in processor performance associated with prior-art approaches. (Image Omitted) Conventional approaches to such interface problems typically require either the insertion of microprocessor wait states, which are some multiple of the microprocessor clock, or the reduction of the microprocessor clock frequency to match the slowest attached component. Instead of adding clock cycles or lowering the clock frequency, this design allows the duration of each clock pulse to be dynamically varied to fit the component accessed. This matches the microprocessor and each attached component with a minimal loss in performance.