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Browse Prior Art Database

Pipeline Memory System for Drams

IP.com Disclosure Number: IPCOM000034926D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
O'Neil, EF [+details]

Abstract

A pipeline system is shown which minimizes the precharge time taken to accommodate re-write, restore, and refresh in a dynamic random-access memory (DRAM), such that the cycle time can be less than the access time. (Image Omitted) As DRAM density increases with each new generation, the die size increases, feature geometries decrease, and faster access times are featured. With increasing density/performance requirements, arrays are broken into smaller sub-arrays to maximize efficiency; however, device channel length scaling does not provide for sufficient access and cycle improvements. A method is shown for a pipelined memory systems where the cycle time can be less than the access time. In conventional DRAM operation, word and bit addresses are timed via a set of control signals, i.e.