Browse Prior Art Database

On Chip LSSD Clock Generator With Zero Gap Between Master to Slave Clocks

IP.com Disclosure Number: IPCOM000034929D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Mueller, KD Peter, JL [+details]

Abstract

The objective is to provide LSSD (level-sensitive scan design) clocks without any timing degradation with the design of a dedicated clock driver book that can be integrated within the register layout. The proposed solution allows: 1. An improvement of the chip performance up to 30% compared to the usual approach where the clock generation of a complete card is centralized in a dedicated 'Clock Chip' and then distributed to each latch. This improvement is achieved by the suppression of all timing skews that the usual approach induced both on the card clock distribution and on the 'on-chip' clock distribution before the clock signals are reaching the latch inputs. 2. An unique implementation applicable to any LSSD master/slave design. 3.