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Versatile Row Redundancy Scheme for High Performance Random Access Memories

IP.com Disclosure Number: IPCOM000034935D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Morrish, JR Thoma, EP [+details]

Abstract

A method is shown for utilizing redundant rows in any of several different array blocks of a semiconductor memory as replacements for defective row, allowing more flexibility and productivity. This row redundancy implementation scheme affords the performance gained by using a replacement row from an adjacent array and also limits the number of selected arrays to conserve chip power. Versatility is built into the implementation by increasing the number of available replacement rows for each array section without increasing the total number of redundant rows on a chip. Referring to the figure, each memory array includes two redundant rows and a redundant row decoder (RD) per block. Also, each array has a separate clock to control array functions, i.e., set, restore, precharge, etc.