Browse Prior Art Database

Memory Architecture With Flexibility in Bit-Wide Outputs

IP.com Disclosure Number: IPCOM000034947D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Miller, CP Nguyen, Q [+details]

Abstract

A memory architecture is shown which can operate with single or multiple bit outputs by transforming the internal architecture. By providing a single memory chip with multiple modes of operation, a wide range of bit-wide customization can be satisfied with a single design and also simplify demands made upon manufacturing. A memory architecture is shown which can be modified by program control to provide the most common modes of operation, i.e., X1, X2, X4, X8,...etc. without the use of data gates. A memory architecture with X1 and X4 options is shown as an example in the figure. Note that each memory array I/O port, I/O 1, I/O 2,.... ..etc., has its own data latch 10 and control circuitry 11.