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Improved Mcleod Loops for MOS Testing

IP.com Disclosure Number: IPCOM000034960D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Turner, ME [+details]

Abstract

An extension of the McLeod Loop Methodology is disclosed which uses a dominant set-reset latch, such as the critical gating function, rather than an OR gate as in the prior art, to facilitate independent characterization of rising and falling delays of inverting logic functions. McLeod loops are modified ring oscillators used to extract logic gate rise and fall delays to characterize many bipolar technologies. Positive logic (AND, OR) is readily available in bipolar technologies; however, there are no positive logic primitives available in MOS technologies. A solution is shown for characterizing strictly negative logic (NAND, NOR) of MOS technologies using McLeod loops to obtain separate rise and fall delays. Fig. 1 shows the basic circuit configuration of the McLeod loops.