Browse Prior Art Database

Two Mask Process for Making Borderless Openings to Three Different Levels Within a Microcircuit

IP.com Disclosure Number: IPCOM000034963D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Koburger, CW Luce, SE [+details]

Abstract

A two mask process is described to create openings through a planarized insulator (1) to a non-planar region for deposition of a conductive strap, (2) to a diffusion for a contact opening, and (3) to a polysilicon conductive line. The masks are designed to be "borderless", i.e., without sacrificing density, they are designed to prevent hole overlap onto adjacent polysilicon wiring when normal misalignment occurs. Referring to Fig. 1, a trench in silicon substrate 4 has thin insulation 2a on its sidewalls and is filled with conductive polysilicon 2b. Conductive polysilicon lines 6 and 8 are formed on gate insulation 10. Thin sidewall insulation 12 is grown on the lines 6 and 8 after line etching and thick top surface insulating film 14 is deposited before line etching.