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Pseudo Nibble Parity for Fast Shifter Parity Predict

IP.com Disclosure Number: IPCOM000034985D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Freerksen, DL Stunkel, CB [+details]

Abstract

Maintaining byte parity is a common method of error checking for multi- byte registers. When registers such as these are used as inputs for arithmetic, prediction of the output parity bits can be made using an input data register and input parity. In floating point arithmetic hardware, a common arithmetic operation is to shift the fraction to the left or to the right. The shift amount might be as few as zero, or as many as 56 for a double precision number. The most common method of performing a fraction shift is to break the shift down into three steps - a rough shift, a medium shift, and a (Image Omitted) fine shift. - The rough shift performs a shift of 0, 16, 32 or 48. - The medium shift performs a shift of 0, 4, 8 or 12. - The fine shift performs a shift of 0, 1, 2 or 3.