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Storage Subsystem Combined Header/Data Transfer Technique

IP.com Disclosure Number: IPCOM000034986D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Gibson, KP Huss, FL Triebenbach, JL [+details]

Abstract

The Storage Subsystem provides a host system with access to DASD devices formatted in 520 byte sectors. Each sector consists of an 8 byte header and 512 bytes of data. The technique described here transfers the headers and data in a single operation. Normally, headers and data are transferred to separate buffers in the Storage Subsystem and are then transferred to the host system in two separate DMA operations. The storage subsystem hardware can transfer up to 4K bytes to the host before reinstruction is required. The overhead for the header transfer doubles the time needed to instruct the hardware to perform the DMA for transfers of 4K or less. The Storage Subsystem hardware architecture provides separate DMA (direct memory access) and microprocessor buses.