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Micro-Ultrasonic Flattening Assembly

IP.com Disclosure Number: IPCOM000034989D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Handford, EF Lidestri, KA Puttlitz, KJ Seshan, K [+details]

Abstract

A proposal suggests use of an ultrasonic micro-flattening level assembly for flattening of solder at small component sites on multi-chip carriers. Existing procedures for component replacement on multi-chip carriers use infrared heating to remove the component and then copper-block dressing to remove residual solder from the substrate. As module designs incorporate closer spacing of features, this technique becomes more difficult to use because of insufficient clearances. When a component is removed from a site anywhere from 40-60% of the solder remains on the substrate. With close tolerances of the surface features, adequate dressing is not always easily achieved. The residual solder forms nodules when it resolidifies and attempting to align or place the replacement component on such a surface is quite difficult.