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Micro-Miniature Solder Flattening Assembly Disclosure Number: IPCOM000034991D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28

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Erk, EA Lidestri, KA Puttlitz, KJ Wenskus, H [+details]


A procedure has been developed for flattening of solder at small sites when replacing components on multi-chip carriers. This technique is especially desirable in those devices where space limitations are critical. Existing procedures for component replacement on chip carriers use infrared (IR) heating to remove the component and then copper-block dressing to remove residual solder from the substrate. As module designs incorporate closer spacing of features, this technique becomes more difficult to use because of insufficient clearances. When a component is removed from a site anywhere from 40-60% of the solder remains on the substrate. With close tolerances of the surface features, adequate dressing is not always easily achieved.