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Streamline High-Speed Buffer Control Circuit for Minimal Latch Usage With LSSD Testability

IP.com Disclosure Number: IPCOM000034996D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Abler, JM Burmester, R Reno, DD [+details]

Abstract

A buffer control circuit is implemented following LSSD design rules. A cell savings and cycle time reduction is accomplished by using both the latch 1 and latch 2 sections of each LSSD latch as separate latches. The amount of cell savings and cycle time reduction is dependent upon the size and depth of the buffer. Refer to the equations below to determine their benefit to a particular implementation. This design incorporates L2* latches, which allow the user to supply separate functional clocks to the different buffer stages. Using a 4-Deep, *-Wide buffer, the following example has been created, which can be seen in the figure above. The design is separated into two sections: 1. Control Section 2.