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Test Logic for Timer Verification Disclosure Number: IPCOM000034998D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28

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Kuhlman, CL [+details]


This invention describes a method to test a 3-second timer efficiently during chip manufacture, and how to verify correct operation of the timer during the diagnostic checkout at system power on time without waiting the full 3 seconds. The description of the hardware to support the unique method of testing the timer is as follows. As shown in the figure, the test logic includes 1. Three microcode addressable bits for timer test mode, timer reset, and timer test OK, 2. Logic to break up the timer into 7-bit sections, and 3. Error-detection logic. The test mode bit A being set forces the 28-bit timer into 7-bit sections and also forces the carry-in to each section to be active. This causes all sections to count together.