Base Register Buffer to Eliminate Address Generation Time in IBM System/370 Architectures
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
A base register buffer mechanism is described herein which shortens the execution time of most RX, RS, SS, SSE, SI, and S instructions in the IBM System/370 processors by decoding the instruction and doing the address generation for a memory operand concurrently. In most programs a single register is used as the base register repeatedly, and its contents change rather infrequently. While generating memory addresses, the time required for fetching the contents of the base register from the register file can be eliminated from the execution time of the instruction, if the address generation unit could save the contents of the base register it uses, and reuse this value whenever possible. The figure shows the proposed base-register buffer mechanism.