CMOS Self-Timed Sense Amplifier Circuit
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
A sense amplifier for static random-access memories using complementary metal oxide semiconductors and timed from the accessed wordline provides reliable, high-speed operation over wide parameter variations using a setting signal with slow and fast setting slopes and decoupling devices. In Fig. 1, assume row decoder 1 and column decoder 2 are selected for a read. Wordline 3 will go high and the gates of the n-channel bit switch devices 4a and 4b will go high and the gates of the p-channel bit switch devices 5a and 5b will go low. This is in the direction to turn on the complementary bit switches. Bit lines 6 and 7 and input/output (I/O) lines 8 and 9 are initially high. Assume bit line 6 (Image Omitted) is discharged by the selected cell 10.