Reduce Peak Electric Field in Semiconductor Junctions
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
This article describes a design method that lowers the peak junction field without degrading the carrier transit time across the junction. Fig. 1 shows the schematics of the collector-base junction impurity profile and the electric field distribution of a conventional bipolar transistor. An insertion of a lightly-doped layer, which is slightly narrower than the depletion-layer width of the original junction, lowers the peak electric field by about a factor or two (Fig. 2). As long as the carrier velocity is in saturation, e.g., the field is mostly greater than 40 KV/cm in silicon, the carrier transit time across the junction remains unchanged. Other implementations of this scheme are shown in Fig. 3.