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Shared Addressing Unit for Jump State Controller and Multiple Rams With Minimal Complexity Control Logic Disclosure Number: IPCOM000035036D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28

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Locke, ME [+details]


The design of digital signal processors with multiple RAMs/buses involves a tradeoff between instruction complexity, instruction length, and instruction efficiency. A large number of index registers for each RAM, each with an immediate offset provides optimum instruction efficiency. Such a solution requires a long instruction word to control the index registers and provide the immediate offsets. Substantial hardware is required to implement the index registers. This article is for an architecture which achieves near optimum instruction efficiency for digital signal processing tasks with substantially reduced instruction complexity as compared to the optimum implementation. The figure depicts the address generator architecture.