Browse Prior Art Database

Hardware to Syncronize Service Requests From Multiple Devices With Equal Data Rates but Asynchronous Timing

IP.com Disclosure Number: IPCOM000035038D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Eaton, GA Locke, ME [+details]

Abstract

Central processing equipment often needs to multiplex together data from digital lines that operate at the same data rate, but have random phase. This occurs any time voice or data is required by some central processing unit and multiple digital interfaces are used to connect to the environment. This problem is complicated by the fact that the digital receivers invariably have some phase jitter, so that the phase relation between incoming data on various lines is variable. Each link generates a strobe called CSYNCH to indicate data transfer. Data is being transferred into the shift registers when CSYNCH indicates that the transfer of one byte is complete. Each of the CSYNCH signals are periodic with some phase-locked loop jitter, but with the same period. A pair of flip-flops per link is used to keep the link state.