Floating-Point Performance Model for a Risc-Based System
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28
A technique is described whereby floating-point performance model architecture is provided for reduced instruction set computer (RISC)- based systems and extended RISC based systems. The concept is intended to enable programmers, writing implementation software, to have a common model, so as to optimize floating-point compilers. It is unique in that it provides an evaluation tool for analyzing both software design and hardware operational performance. Typically, RISC systems have an interdependence between the physical hardware and operational software. Since most floating-point software is produced by compiling code, compilers must be developed so that they can take full advantage of the RISC floating-point arch itecture in order to produce code which will have superior performance.