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Efficient Add/Sub/Cmp Algorithm for IEEE Floating Point Operands

IP.com Disclosure Number: IPCOM000035063D
Original Publication Date: 1989-May-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Brown, JD Stunkel, CB [+details]

Abstract

An algorithm and a hardware implementation of the algorithm that performs IEEE floating point addition and subtraction is constructed here. When taking the difference between two numbers, the algorithm selects between ones and twos complement arithmetic to guarantee a signed magnitude answer will always be generated. This selection removes the need for twos complementing the result and improves the performance of the algorithm. The figure is a block diagram illustrating the fraction dataflow for the hardware implementation of this process. The ALIGNER selects the operand fraction with the smaller exponent. The ALIGNER then shifts the fraction the correct number of bits to the right. The output of the aligner is passed to the "right" input of the ADDER.