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TIMING Generation LOGIC for DOT Matrix Printer

IP.com Disclosure Number: IPCOM000035123D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Hisano, T Katoh, H [+details]

Abstract

A timing generation logic for the dot matrix printer is provided without using any timing counter or one-shot timing logic, but using a memory device as a pattern generator which outputs a desired control pattern sequentially. As the control data is to be prepared for each dot pin, the drive timing can be generated individually. Thus, this logic method enables compensating print registration due to vertical misalignment of the dot pin of the print head. Also, multi-phase firing of the head pin is easily performed which is effective to reduce impact noise and power unit load.