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Asynchronous Interface Transfer Signal and Delay Line Checking Disclosure Number: IPCOM000035166D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28

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James, PN [+details]


The logic described below samples an asynchronously generated transfer signal line and tests it for stuck-on conditions due to logic errors, or improper delay line tolerances or orderings.