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The logic described below samples an asynchronously generated transfer signal line and tests it for stuck-on conditions due to logic errors, or improper delay line tolerances or orderings.
English (United States)
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Asynchronous Interface Transfer Signal and Delay Line Checking
The logic described below samples an asynchronously generated transfer
signal line and tests it for stuck-on conditions due to logic errors, or improper
delay line tolerances or orderings.
The transfer signal latch is the first and primary asynchronous latch that
initiates the handling of a byte of data on an original equipment manufacturer's
interface (OEMI) channel. This latch is set in many ways and in various modes,
but primarily it is set by the combination of a system clocked generated Transfer
OK line being up and an incoming asynchronous Service In line or Data In line
coming in. The SIG latch, being asynchronous, is synched up to system clocks
via some demetastability logic. This synched up SIG line is called a Detected
Transfer Signal line. The SIG latch also initiates the off chip Delay line
sequences via the SSDRIVEO latch. The delay lines are a series of timed pulses
that are returned to the PIA chip from an external source. The pulses generate
two asynchronous clocks that are used to clock data between the external
asynchronous control unit and the PIA chip. They are also used to set the
corresponding outbound tag
line. These timed pulses are set to allow for data deskewing and various pulse
tolerance specifications set up by the OEMI standard. If these delay lines are
received out of specification, or in an improper order, or if the SIG latch sticks on,
severe channel er...