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High-Speed Error Correction Coding

IP.com Disclosure Number: IPCOM000035169D
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Bossen, DC Chen, CL [+details]

Abstract

Most error-correcting codes (ECC) used in semiconductor memory systems are the SEC-DED codes that correct all single errors and detect all double errors in an ECC code word. The error correction for these codes is typically implemented in the following three sequential steps: 1. The syndrome is generated from the word read from the memory. 2. The syndrome is decoded using a set of AND gates to generate error signals. (There are as many error signals as the number of data bits.) 3. Each of the error signal is XORed with its corresponding data bit for the error correction.