Address Chaining Scheme to Provide Simultaneous-Multiple-Write Capability for Memory
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
This disclosure describes a method to implement random access memory (RAM) with the capability of writing the same contents to multiple consecutive locations simultaneously. This feature substantially increases the memory updating speed, and thus reduces the potential bottleneck of the speed in applications such as controlling time-division- multiplex (TDM) switches.