Page Transfer Hardware Assist for Digital Signal Processor
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
Most of current generation digital signal processor (DSP) devices have a limited data addressability. For example the 10 MHz IBM DSP can address 4 K half-word (12 bits). For addressability extension, a paging register is used, which contains the most significant bits (MSBs) of the address, which is loaded via a store operation by the signal processor. This generates overhead cycles in the case of data transfer from one page to another. Fortunately, in most of signal processing functions, transfers between pages are implemented on a buffer basis. So, one can suppress the overhead due to the paging register loading and reloading operations, through a simple mechanism based on a control register CNTREG connected to an I/O of the DSP.