Avoiding Address Generation Delays Using the Delay Overlap Prefetch Table
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
A history-based, table-driven approach to overlapping certain I (Instruction) Unit delays in high performance computers with target instruction access delay for the next taken branch has been shown in [*]. This Delay Overlap Prefetch Table (DPT) is accessed when an address generation interlock, among other conditions, is detected in the I Unit; it delivers the target address of the next taken branch based on previous execution. Thus, the interlock delay is overlapped with the branch target access delay, and there is no delay when the taken branch is subsequently decoded.