Level-Sensitive Scan Design Digital Portion of Phase-Locked Loop and Data Separator
Original Publication Date: 1989-Jun-01
Included in the Prior Art Database: 2005-Jan-28
This article describes the use of level-sensitive scan design (LSSD) methodology to implement the digital portion of an analog phase-locked loop (PLL) and data separator. This LSSD is equivalent to a design utilizing edge-sensitive latches but has the advantages provided by LSSD high testability and no race conditions.