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By using N-channel pull-up devices to differentially write into a complementary metal oxide silicon (CMOS) static latch, fast writing speed is achieved.
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Fast Write Circuit for a Complementary Metal Oxide Silicon Static Latch
By using N-channel pull-up devices to differentially write into a
complementary metal oxide silicon (CMOS) static latch, fast writing speed is
Referring to the figure, a restore pulse R is input to differential gate logic
block 2 in a standard manner. Outputs from block 2 are connected gates of N-
channel transistors T1, T2, T3, and T4 as shown. Thus, a low level is written into
the CMOS latch (enclosed in the dashed rectangle) with transistors T1 or T2 and,
simultaneously, a high level is written with transistors T3 or T4. The high level is
Vh = Vdd - Vtn, where Vdd is the high supply voltage and Vtn is the threshold
voltage of the N-channel devices. Differential logic gate outputs are restored to
ground which allows the CMOS latch to be written from other sources 4 and 6
through transistors T6 and T5.
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