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Efficient Multiple Selection for Floating Point Algorithms Disclosure Number: IPCOM000035338D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28

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Norris, LR [+details]


This method reduces the number of gates required to implement the logic feeding the mantissa adder in a chip which shares this adder for the add, multiply, divide and square root floating point functions. This is done by making a slight modification to the division algorithm which, in turn, reduces the number of multiples of the operands which are required. This process will also reduce the width of the mantissa adder. (Image Omitted)