Browse Prior Art Database

BICMOS LATCHUP PREVENTION SCHEME

IP.com Disclosure Number: IPCOM000035353D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Schmerbeck, TJ Buchholtz, TC Richetta, RA [+details]

Abstract

This is a general circuit design scheme to prevent latch-up on chips containing both high current bipolar and CMOS circuits. The normal precautions of not pulling any chip pads above the most positive chip supply or below the most negative chip supply must still be followed. If the subcollector is not buried during the ACMOS process, the bipolar NPN transistors saturate early (at over a volt collector to emitter voltage at rated current). The absence of the subcollector also makes it easier to drive saturation currents into the chip substrate and thus have the potential for latchup. In general, any BI-CMOS process is subject to latchup if substrate currents get large enough.