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Semiconductor Isolation Structure and Process Using Epitaxy Overgrowth

IP.com Disclosure Number: IPCOM000035358D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Arienzo, M Lu, NC [+details]

Abstract

A technique is described whereby a semiconductor isolation structure and process provides device isolation space smaller than the minimum lithography feature size. By using lateral epitaxy overgrowth, a reversed "T" shape is achieved, requiring shorter temperature cycles and no extra mask steps when compared to previous processes.