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Speed/Power Improvement for Large Fan-In Emitter Coupled Logic Decoder Circuits

IP.com Disclosure Number: IPCOM000035362D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Wendel, DF Wiedmann, SK [+details]

Abstract

A circuit technique which improves the speed and power consumption of emitter coupled logic (ECL) decoders, as used in bipolar semiconductor arrays, is described. The circuit improvement enables a large number of fan-ins with relatively lower power consumption and improved delay. (Image Omitted)