SELF-ALIGNED SUB-HALF MICRON GALLIUM ARSENIDE MESFETs AND SILICON MOSFETs
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
A technique is described whereby an improved fabrication process provides self-aligned sub-half micron GaAs MESFETs and Si MOSFETs by avoiding multi-level resists, lift-off techniques, as well as E-beam and X-ray lithographies. Described is a process that utilizes both optical and "chemical" lithography to fabricate sub-micron gate GaAs MESFETs and Si MOSFETs in one mask step.