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Data Buffer With Shared Parity Module Disclosure Number: IPCOM000035365D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28

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Kaffashan, A Oman, PW Vasquez, AE [+details]


Multiplexing the parity module, by accessing a single high-speed buffer twice each cycle to generate two parity bits, makes it possible to make a data buffer array from available storage array modules even though they are not optimum in configuration.