Method of Reducing Emitter Coupled Logic Power Consumption by the Use of a Complementary Emitter-Follower Driver
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Disclosed is a method of reducing the power consumption of Emitter Coupled Logic (ECL) by using a complementary emitter-follower driver. This approach reduces the ECL power consumption by about 30-35% and enhances the driving capability of the ECL circuits. Fig. 1 and 2 illustrate alternative embodiments of an ECL NOR circuit including emitter-follower driver circuitry. The circuit of Fig. 1 basically resembles a conventional ECL NOR/OR gate except that additional emitter-follower transistors T4 and T5 are added and used to drive pull-down PNP transistors T6 and T7. In Fig. 1, pull-down PNP transistors (T6, T7) and pull-up NPN transistors (T8, T9) are configured as complementary emitter-follower drivers.