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Column-Address Controlled Sense Amplifier Latching Circuit for DRAM

IP.com Disclosure Number: IPCOM000035397D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Dhong, SH Lu, NCC [+details]

Abstract

A technique is described whereby a column-address controlled sense amplifier latching circuit improves operational performance of high- speed dynamic random-access memory (DRAM) without increasing the access or cycle time of the device.