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Redundancy and Logic-Ec Scheme for Passive Superchip

IP.com Disclosure Number: IPCOM000035652D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28

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Haug, W Klink, E Schettler, H Stahl, R [+details]


A method is described which allows increasing the process yield of silicon carriers by using a system of redundant wires.