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Precision Delay Circuit Disclosure Number: IPCOM000035668D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 31K

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Dreps, DM: AUTHOR [+1]


Disclosed is a circuit that allows precise edges to be granted for clocking purposes.

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Precision Delay Circuit

Disclosed is a circuit that allows precise edges to be granted for clocking purposes.

The circuit is shown in the figure. The components of the circuit are explained. Rext and Cext are off-chip components that are used to set an RC time constant. The five resistors (R) from Vcc to ground are of the exact same design spaced in close proximity on-chip to track. Three to X resistors may be used versus the five shown. The circuit disclosed acts as a voltage follower which is switched on and off. The input to the comparator is differential while the output may be single ended or differential to drive an output stage. The switching current source is supplied by the input stage to this block. The bias of the voltage follower is set to insure the emitter-coupled pair is being operated in the linear mode when the bias is switched on. The precise time is set using Equation 1. Vcext(t) = Vcc(1-exp(-td/Rext*Cext)) (1)

Vcext will be clamped at (2/5)*Vcc by the disclosed circuit while the circuit waits for a timing edge. When a timing edge is received the switching current source is disabled and Vcext begins to rise. The time delay is the time required for the Vcext to rise from (2/5)*Vcc to (4/5)*Vcc. Since the circuit of the figure is a bridge, the temperature and Vcc sensitivities are nulled. The circuit disclosed minimizes the variation around (2/5)*Vcc to be the technology VBE matching + VOS. VOS is the offset voltage of the disclosed circuit. The...