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Prediction of Shift Left Single and Shift Left Double Overflow Condition

IP.com Disclosure Number: IPCOM000035677D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Huffman, AE Jabusch, JD [+details]

Abstract

In IBM System/370 and System/370 Extended Architecture there is an overflow condition code for the instructions Shift Left Single (SLA) and Shift Left Double (SLDA). The SLA and SLDA instructions are arithmetic shifts which means the sign bit (the high-order bit of data) does not participate in the shift. The overflow condition code is defined as the detection of any bits being shifted out that are different from the sign bit. This condition is easily detected if the shift is performed with shift registers. However, most processors perform this shift in a single clock cycle because it is faster.