Simconvert - an Automated Method for VLSI Simulation to Test Vector Conversion Using Test Program Information
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
This article describes a method that automatically converts very large- scale integration (VLSI) design system simulation files to VLSI test system vectors using timing and sampling information (the AC specification) found in the test program information. Input files required by SimConvert: Device simulation file - a file containing the state of each pin of the device. This file is obtained from VSLI device simulator which outputs the states and the time at which they occur in ascending order. State or Cycle file - a file containing a list of states or cycles of the device in the sequence that they occur in the simulation file. Output files created by SimConvert: Vector file - VSLI test vector for the target VLSI test system. Error file - a file containing problems and diagnostic information found during the vector conversion.