Data Flow Checking Device for Address Generation and Address Path
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
This article describes an arrangement for verifying the ability of one card to read the memory on another card. It verifies the data path, the address path, and the address generation. Specifically, it checks the ability of a Printer Data Card to unload data correctly from Raster Buffer Memory in an All-Points-Addressable printer controller. This arrangement uses software and a minimal amount of hardware. This test is part of the power-on diagnostics which are run on the printer. The extra memory modules, extra logic, and wider bus associated with parity are avoided. Little hardware is required beyond the existing, functional hardware so the arrangement provides significant cost savings. The simplicity of the design reduces the probability of failure by the error-checking logic.