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Timing Verification for Macros With Usage Dependent Constraints

IP.com Disclosure Number: IPCOM000035819D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 4 page(s) / 48K

Publishing Venue


Related People

Elder, WH: AUTHOR [+2]


An algorithm is shown that allows timing verification of a single physical VLSI macro that has multiple logical applications on a chip.

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Timing Verification for Macros With Usage Dependent Constraints

An algorithm is shown that allows timing verification of a single physical VLSI macro that has multiple logical applications on a chip.

The characteristics of a macro can vary with its logical application and typical macros requiring this capability are those classified as storage elements, i.e., random-access memories (RAMs), level- sensitive scan design shift register latch (LSSD SRL) and registers whose delay between two pins is determined by some other controlling signal input, e.g., a shunt path in a logical macro.

A stand-alone analysis tool developed for FET technologies called Early Timing Estimator (ETE) is utilized to provide the logic/chip designer with timing information at various stages throughout the design process. Logic is supplied to ETE through a logic description language and ETE carries out both delay calculations and timing verification by referencing formatted technology data. The results allow designers to modify the logic and/or physical design with a high degree of confidence in the chip's performance. Circuit delays are described through technology data by relating an input pin to an output pin. The data, in part, contains equation coefficients for each unique circuit and performance level in the technology offering.

ETE calculates rising and falling delays and output transition times from the following standard FET equations: Td = (K1 + K2*CL)*Tx + K3*CL**2 +K4*CL + K5 where:

Td = delay value (TPLH, TPHL, TRO, TFO)

K1,....,K5 = delay equation constants in ETE


CL = net loading capacitance (in pf).

Tx = input rise or fall time.


TPLH = time to propagate from low to high at


TPHL = time to propagate from high to low at


TFO = rising output transition.

TFO = falling output transition.

Once the delays are known for all signals arriving at a clocked element, ETE verifies that the proper relationship exists between the data and control signals. Specific timing checks for a circuit are defined by the technology data. Possible timing checks for a circuit include data setup/hold time, clock pulse width and clock separation.

A macro can be selectively modeled for ETE to represent unique conditions surrounding a possible range of logical applications. The different models are known as "delay modes". With this option, multiple models and checking rules for a macro/circuit can be stored, accessed and used selectively by the designer. Simple primitive logic circuits, i.e., NAND, NOR, AOI, etc., are represented by a set of delay equations which specify the delays from input to output. As more


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complex VLSI circuits are developed, large macros result which can contain multiple delay paths between a single input to output pin pair.

Referring to Fig. 1, there are two possible delay paths of interest for the pin pair AO to 10, thus requiring the use of delay modes. In the normal mode of operation, this macro exhibits delay...