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The control system described in this article serves to control the transition detection (XDET) data acquisition mode designed for the functional self test chip (FSTC) prototype.
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Transition Detection Control Subsystem for the Functional Self-Test Chip
The control system described in this article serves to control the transition
detection (XDET) data acquisition mode designed for the functional self test chip
The transition detection circuits in the FSTC prototype consist of SSI
components. The control logic will perform the following: 1. Clear the XDET
internal registers prior to data acquisition. This can be accomplished by pulling
the master reset of the XDET low. 2. Generate the clock signal for acquisition.
The data will be shifted in serially at the rising edge of the clock. The function of
each block is described below.
Four active low clear signals (xclr_1 to xclr_4) are generated
asynchronously when the clear encoding from the FST control register
is received. All four signals are identical. Four clear signals are
needed because of fan_out requirements. The reduced equation for
xclr_1 is listed below.
xclr_1 = clear * xdet + clear * all
XDET Clock Generator
XDET clock signals are required for data acquisition mode. In the
asynchronous acquisition mode, the XDET clock is the result of gating the board
under test's (BUT's) clock with the control encoding and the acquistion enable
(acqen) signal. In the counter controlled acquisition mode, the XDET clock is a
gating product of the BUT's clock, control encoding, acqen signal, start counter
zero (z0) and the stop counter not zero (µz1) signal. Th...